1. Field of the Invention
The invention relates in general to a method for reading and programming a memory, and more particularly to a method for reading and programming a memory, which corrects the program verify (PV) level, erase verify (EV) level or read reference level of the first-side and the second-side of each cell by considering an array effect, a second-bit effect and a neighbor-bit effect.
2. Description of the Related Art
In the traditional flash memory, such as a multi-level cell (MLC) memory, has two sides in each memory cell and each side, having at least one bit, is set to have a preset PV level in a program operation and have a preset reference level for read/PV/EV in a read operation. For example, if the MLC memory has one bit in each side of the memory cell, there are four possible Vt distributions for each cell: “11”, “10”, “01” and “00”. These reference levels are normally kept at a constant value in the whole program or read operation without considering the cell characteristics of the neighboring cells.
FIG. 1A shows an example of the second-side and neighbor side for a first-side of a specific cell to be programmed or read during source side sensing. As shown in FIG. 1A, supposed the first-side B2 of the cell B is to be programmed or read, the other side B1 of the cell B is defined as a second-side of the first-side B2.
When the memory array becomes larger, the sensed threshold voltage (Vt) level of each cell will deviate from an initial Vt level by a shift value due to a parasitic-resistance effect (an array effect), a second-bit effect and a neighbor-bit effect existing in the cell current sensing path as shown in FIG. 1B. The second-bit effect and neighbor-bit effect will be more and more significant when each cell of the memory is scaling down. As a result, the sensing window SW1 between Vt distributions “11”, “10”, “01” and “00” of the memory becomes smaller than the sensing window SW0 without Vt shift (as shown in FIG. 1B) and thus the memory cycling margin is greatly reduced.